SevenSegmentTestbench

Source: Lab3b/SevenSegmentTestbench.sv (modified 2025-10-23 15:48)

/*
 * ECE 272 Lab 3b
 * Seven Segment Testbench Skeleton File
 *
 * Adapted from Harris & Harris "Digital Design and Computer Achitecture"
 * Example 4.38 "Self-Checking Testbench" (Page 215)
 *
 * Author(s): Quinn Yockey
 * Last Modified: 21 February 2025
 */

/* IMPORTANT! Read the comments carefully. They are included to help you! */

/*
 * Instructions:
 * 1. Open the course textbook. This file is based on Example 4.38,
 * which will help you complete this exercise.
 * 2. Tasks are marked with a number in brackets (e.g., [1]). Each has a
 * corresponding TODO comment to replace with SystemVerilog code.
 */

module SevenSegmentTestbench();

    /*
     * Create signals to connect to the SevenSegmentDecode module:
     *
     * - `digitTest`: Drives the `digit` input in SevenSegmentDecode.
     * - `segmentsMeasured`: Captures the `segments` output of SevenSegmentDecode.
     *
     * [1] Define the width of the `segmentsMeasured` signal. Match the width
     * of the `segments` output from SevenSegmentDecode.
     */
    logic [3:0] digitTest; // Input digit to test
    logic [6:0] segmentsMeasured;

    // Declare a 16-element array for expected output values.
    // This declaration must be at the module level.
    logic [6:0] expected [0:15];


    /*
     * Create instance of the device under test (DUT): SevenSegmentDecode.
     *
     * The `digitTest` signal is connected to the DUT `digit` input. This
     * allows the testbench to control the `digit` value in SevenSegmentDecode
     * by changing the value of `digitTest`.
     *
     * A signal can be connected to a module input or output port by specifying
     * the module port (ex: `digit`) and then stating the connected signal
     * (ex: `digitTest`) in parenthesis. Note that the syntax used here differs
     * from syntax used in the textbook.
     *
     * [2] Connect `segmentsMeasured` to `segments` output. This allows the
     * testbench to read the `segments` value of SevenSegmentDecode by
     * checking the `segmentsMeasured` signal.
     *
     * Note: For those who have taken CS classes, the syntax is similar to
     * passing arguments in a function call.
     */
    SevenSegmentDecode dut(
        .digit(digitTest),
        .segments(segmentsMeasured)
    );

    /*
     * Testbench Overview:
     *
     * A testbench operates through a series of tests. The idea is to validate
     * that for a given input, a module yields the correct output.
     *
     * In this case, the testbench will check each 4-bit number from 0x0 to 0xF
     * and confirm that SevenSegmentDecode module outputs the correct signals to
     * light up the 7-segment display.
     *
     * Each test has the following structure:
     * [3] Assign a test value to `digitTest`.
     * [4] Delay for 10 ps to allow the output to update.
     * [5] Compare `segmentsMeasured` to the expected value of `segments`.
     * This expected value should be hard-coded into the program.
     * [6] Print an error message if the output is incorrect.
     *
     * Execute this process for all possible inputs 0x0 though 0xF.
     */

    // Initialize the expected output array. This is an initial block that runs once.
    initial begin
        expected[ 0] = 7'b1000000; // 0
        expected[ 1] = 7'b1111001; // 1
        expected[ 2] = 7'b0100100; // 2
        expected[ 3] = 7'b0110000; // 3
        expected[ 4] = 7'b0011001; // 4
        expected[ 5] = 7'b0010010; // 5
        expected[ 6] = 7'b0000010; // 6
        expected[ 7] = 7'b1111000; // 7
        expected[ 8] = 7'b0000000; // 8
        expected[ 9] = 7'b0010000; // 9
        expected[10] = 7'b0001000; // A
        expected[11] = 7'b0000011; // B
        expected[12] = 7'b1000110; // C
        expected[13] = 7'b0100001; // D
        expected[14] = 7'b0000110; // E
        expected[15] = 7'b0001110; // F
    end
     integer i;  
initial begin

    // 执行一个预先的复位或等待，确保 DUT 启动稳定
    digitTest <= 4'h0;
    #10; // 确保第一个 0x0 测试前有一个稳定状态

    // [7] 使用一个循环测试所有输入 0x0 到 0xF。
    for (int i = 0; i < 16; i++) begin
        
        digitTest <= i[3:0]; 
        
        // [4] Delay for 10 ps to allow the output to update.
        // 等待 10 ps，给 DUT 足够的时间来处理新的输入 i 并更新 segmentsMeasured。
        #10; 

        // [5] Compare `segmentsMeasured` to the expected value.
        // [6] Print an error message if the output is incorrect.
        if (segmentsMeasured !== expected[i]) begin
            $display("ERROR: digit=0x%0h expected=%b got=%b", i, expected[i], segmentsMeasured);
        end
    end

    /* === End of Simulation === */
    $display("Simulation complete.");
    $stop;
end



endmodule